1. Field of the Invention
This disclosure relates generally to memory devices, particularly memory devices having an open bit line architecture, and methods of testing memory devices.
2. Description of the Related Art
In general, in a memory device having an open bit line architecture, sense amplifiers are arranged between sub-arrays. Each of the sense amplifiers is connected to two bit lines, each of which is connected to the memory cells of an adjacent sub-array. However, some of the bit lines located in the sub-arrays at the edges of a memory array are not connected to sense amplifiers (hereinafter referred to as “dummy bit lines”). The dummy bit lines are connected to dummy memory cells.
In a memory device having an open bit line architecture, the bit lines of a sub array are interleaved with each other. One bit line of a sub-array is connected to a sense amplifier on one side of the sub-array, and an adjacent bit line is connected to another sense amplifier on the other side of the sub-array. However, edge sub-arrays have dummy bit lines that are interleaved with normal bit lines. Each of the dummy bit lines is arranged between two bit lines, and each of the normal bit lines is arranged between two dummy bit lines.
In a memory device having a conventional open bit line architecture illustrated in FIG. 1, dummy bit lines DUMMY are always connected to a fixed voltage (typically, VCC/2). A problem arises when a stress test is performed on the sub-arrays of a memory cell.
For example, a test pattern is applied to the memory cell during the test. The test pattern may be set such that it includes random data represented by different voltages such as a supply voltage VCC and a ground voltage VSS. For example, adjacent bit lines BIT and /BIT may be controlled by the supply voltage VCC and the ground voltage VSS, respectively. Writing a test pattern of supply voltage VCC and ground voltage VSS in memory cells during a test is similar to writing data having logic “1” and logic “0” in memory cells during a normal operation. In this manner, bit lines BIT and /BIT connected to a memory cell are controlled by opposite supply and ground voltages VCC and VSS. This stress test is applied to find defects between memory cells or bit lines.
However, in the memory device having a conventional open bit line architecture as illustrated in FIG. 1, dummy bit lines DUMMY are always connected to the voltage VCC/2. The voltage between the normal bit lines 31 of the edge sub-arrays 30 and the dummy bit lines DUMMY can only be controlled by the difference between the voltage VCC and the voltage VCC/2, or the voltage VSS and the voltage VCC/2. This implies that the memory cells or bit lines of the edge sub-arrays 30 undergo only half of the stress that the memory cells or bit lines of non-edge sub-arrays 50 undergo.
As a result, in memory devices having conventional open bit line architectures, the memory cells or the bit lines of the edge sub-arrays 30 are not fully stressed during a test. As a result, defects detectable in non-edge sub-arrays 50 may not be detected in the edge sub-arrays 30.